refactor: 缠论引擎包化与 Web 分层（ECR-001）
将根目录引擎迁入 chanlun/ 并保留兼容 shim；拆分 TF_DF 与 web 服务； 前端模块化；strategies 改用 chanlun 导入；补充 ESS 文档与 golden 回归。 Co-authored-by: Cursor <cursoragent@cursor.com>
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jackyu66git
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import copy
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from typing import Dict, Optional
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from ChanEnum import Chan_FX_TYPE, Chan_KLINE_DIR, Chan_SEG_DIR, Chan_BI_DIR, Chan_ZS_DIR
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import ChanCTime
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from ChanBI import ChanBI
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from ChanBIZS import ChanBIZS
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class ChanSEG():
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def __init__(self, start_bi: ChanBI, index, ddir=Chan_SEG_DIR.UP, pre_end_bi: ChanBI = None):
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self.start_bi = start_bi
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self.start_time = start_bi.start_time
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self.end_time = None
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self.end_bi = None
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self.dir = ddir
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self.low = 0
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self.high = 0
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if self.dir == Chan_SEG_DIR.UP and start_bi:
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self.low = start_bi.low
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else:
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if start_bi:
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self.high = start_bi.high
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self.index = index
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self.pre = None
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self.next = None
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self.bi_list = []
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self.bi_list.append(start_bi)
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self.is_sure = False
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self.sure_time = None
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self.macd_hist = 0
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self.macd_div = 0
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self.start_bi.set_seg(self)
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self.pre_end_bi = pre_end_bi
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if self.pre_end_bi:
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self.ini_seg()
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def ini_seg(self):
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next_bi = self.start_bi.next
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for index in range(self.start_bi.index+1, self.pre_end_bi.index):
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if next_bi:
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self.bi_list.append(next_bi)
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next_bi.set_seg(self)
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next_bi = next_bi.next
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def set_macdhist(self, macd_hist):
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self.macd_hist = macd_hist
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def set_macd_div(self, macd_div):
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self.macd_div = macd_div
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def set_end_bi(self, bi: ChanBI, sure_bi: ChanBI):
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self.end_bi = bi
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if bi and bi.is_sure:
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if self.dir == Chan_SEG_DIR.UP:
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self.high = bi.high
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else:
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self.low = bi.low
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self.is_sure = True
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self.end_time = bi.end_klc.end_time
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if sure_bi.is_sure:
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self.sure_time = sure_bi.sure_time
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self.format_bi_list()
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def pre_set_end_bi(self, bi: ChanBI):
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self.end_bi = bi
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if bi and bi.is_sure:
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if self.dir == Chan_SEG_DIR.UP:
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self.high = bi.high
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else:
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self.low = bi.low
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self.end_time = bi.end_klc.end_time
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self.format_bi_list()
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def set_pre(self, seg):
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self.pre = seg
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def set_next(self, seg):
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self.next = seg
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def set_sure(self, sure_bi):
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if sure_bi.is_sure:
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self.sure_time = sure_bi.sure_time
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self.is_sure = True
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self.format_bi_list()
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def format_bi_list(self):
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self.bi_list = []
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self.bi_list.append(self.start_bi)
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if self.end_bi:
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next_bi = self.start_bi.next
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for i in range(self.start_bi.index, self.end_bi.index):
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if next_bi:
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self.bi_list.append(next_bi)
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next_bi.set_seg(self)
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next_bi = next_bi.next
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def add_bi(self, bi: ChanBI):
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if len(self.bi_list) > 0:
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self.bi_list.append(bi)
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bi.set_seg(self)
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self.end_time = bi.end_time
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self.end_bi = bi
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def cal_bi_zs(self):
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zs_list = []
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if len(self.bi_list) > 3:
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last_zs = None
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if self.dir == Chan_SEG_DIR.UP:
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for index in range(1, len(self.bi_list)):
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bi = self.bi_list[index]
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#print(bi.end_time, bi.next,"UP SEG BI ZS Index")
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if bi.next == None or bi.next.next == None:
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if last_zs and (bi.low > last_zs.zg or bi.high < last_zs.zd):
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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continue
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bi2 = bi.next
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bi3 = bi.next.next
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if len(zs_list) == 0 or (last_zs and last_zs.is_sure):
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if bi3.is_sure and bi3.index <= self.bi_list[-1].index and bi.check_bi_zs_overlap() and bi.dir == Chan_BI_DIR.DOWN:
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zg = min(bi.high, bi2.high, bi3.high)
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zd = max(bi.low, bi2.low, bi3.low)
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gg = max(bi.high, bi2.high, bi3.high)
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dd = min(bi.low, bi2.low, bi3.low)
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zs = ChanBIZS(bi, len(zs_list), Chan_ZS_DIR.UP)
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zs.set_zg(zg)
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zs.set_zd(zd)
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zs.set_gg(gg)
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zs.set_dd(dd)
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zs.add_bi(bi2)
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zs.add_bi(bi3)
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zs_list.append(zs)
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last_zs = zs
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else:
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if bi.index > last_zs.bi_list[-1].index and bi.dir == Chan_BI_DIR.DOWN and bi.is_sure:
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if bi.low > last_zs.zg or bi.high < last_zs.zd:
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#print(bi.end_time, "UP SEG BI ZS End")
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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if bi3.is_sure and bi3.index <= self.bi_list[-1].index and bi.check_bi_zs_overlap() and bi.dir == Chan_BI_DIR.DOWN:
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zg = min(bi.high, bi2.high, bi3.high)
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zd = max(bi.low, bi2.low, bi3.low)
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gg = max(bi.high, bi2.high, bi3.high)
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dd = min(bi.low, bi2.low, bi3.low)
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zs = ChanBIZS(bi, len(zs_list), Chan_ZS_DIR.UP)
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zs.set_zg(zg)
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zs.set_zd(zd)
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zs.set_gg(gg)
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zs.set_dd(dd)
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zs.add_bi(bi2)
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zs.add_bi(bi3)
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zs_list.append(zs)
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last_zs = zs
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else:
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last_zs.add_bi(bi.pre)
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last_zs.add_bi(bi)
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if index == len(self.bi_list) - 1 and last_zs and not last_zs.is_sure:
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#print(bi.start_time, "BI", last_zs.is_sure)
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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else:
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for index in range(1, len(self.bi_list)):
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bi = self.bi_list[index]
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if bi.next == None or bi.next.next == None:
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if last_zs and (bi.low > last_zs.zg or bi.high < last_zs.zd):
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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continue
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bi2 = bi.next
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bi3 = bi.next.next
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if len(zs_list) == 0 or (last_zs and last_zs.is_sure):
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if bi3.is_sure and bi3.index <= self.bi_list[-1].index and bi.check_bi_zs_overlap() and bi.dir == Chan_BI_DIR.UP:
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zg = min(bi.high, bi2.high, bi3.high)
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zd = max(bi.low, bi2.low, bi3.low)
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gg = max(bi.high, bi2.high, bi3.high)
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dd = min(bi.low, bi2.low, bi3.low)
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zs = ChanBIZS(bi, len(zs_list), Chan_ZS_DIR.DOWN)
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zs.set_zg(zg)
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zs.set_zd(zd)
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zs.set_gg(gg)
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zs.set_dd(dd)
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zs.add_bi(bi2)
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zs.add_bi(bi3)
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zs_list.append(zs)
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last_zs = zs
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else:
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if bi.index > last_zs.bi_list[-1].index and bi.dir == Chan_BI_DIR.UP and bi.is_sure:
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if bi.low > last_zs.zg or bi.high < last_zs.zd:
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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if bi3.is_sure and bi3.index <= self.bi_list[-1].index and bi.check_bi_zs_overlap() and bi.dir == Chan_BI_DIR.UP:
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zg = min(bi.high, bi2.high, bi3.high)
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zd = max(bi.low, bi2.low, bi3.low)
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gg = max(bi.high, bi2.high, bi3.high)
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dd = min(bi.low, bi2.low, bi3.low)
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zs = ChanBIZS(bi, len(zs_list), Chan_ZS_DIR.DOWN)
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zs.set_zg(zg)
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zs.set_zd(zd)
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zs.set_gg(gg)
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zs.set_dd(dd)
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zs.add_bi(bi2)
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zs.add_bi(bi3)
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zs_list.append(zs)
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last_zs = zs
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else:
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last_zs.add_bi(bi.pre)
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last_zs.add_bi(bi)
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if index == len(self.bi_list) - 1 and last_zs and not last_zs.is_sure:
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#print(bi.start_time, "BI", last_zs.is_sure)
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last_zs.set_end_bi(last_zs.bi_list[-1], last_zs.bi_list[-1].sure_time)
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#print(self.start_time, len(zs_list))
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#print(self.bi_list[-1].end_time, "end_bi")
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return zs_list
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"""兼容 shim — 请优先 from chanlun import ..."""
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from chanlun.core.ChanSEG import * # noqa: F403
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